This application claims the benefit of Korean Patent Application No. 1999-24158, filed on Jun. 25, 1999, which is hereby incorporated by reference.
1. Field of Invention
The present invention relates to a method of fabricating a thin film transistor, and more particularly, to a method of fabricating a thin film transistor having a silicon film crystallized by sequential lateral solidification.
2. Discussion of the Related Art
A silicon grain grows in a vertical direction of an interface between a liquid phase silicon region and a solid phase silicon region. Sequential Lateral Solidification (hereinafter abbreviated SLS) is a technique of crystallizing an amorphous silicon film by enhancing the size of the silicon grain, which is achieved by having the silicon grain grow laterally to a predetermined length by manipulating the displacement of the energy and irradiation range of a laser beam (Robert S. Sposilli, M. A. Crowder, and James S. Im, Mat. Res. Soc. Symp. Proc. Vol. 452, 956-957, 1997).
SLS enables the fabrication of a thin film transistor (hereinafter abbreviated TFT) having a channel region of single crystalline silicon by forming an SLS silicon film having a very large grain size on a substrate.
FIGS. 1A to FIGS. 1D show steps of fabricating a TFT according to a related art. The left sides of FIGS. 1A-1D illustrate cross-sectional views while the right sides illustrate schematic layouts of a silicon film to show the respective states of silicon.
Referring to FIG. 1A, a buffer layer 10 of silicon oxide is deposited on an insulated substrate 100. Then, an amorphous silicon film 11 is deposited on the buffer layer 10.
Referring to FIG. 1B, the amorphous silicon film 11 is crystallized by SLS to form an SLS silicon film 12 having silicon grains 12G which are grown to an enormous size. The SLS silicon film 12 is attained by having the silicon grains 12G grow to a specific direction. In the drawing, the silicon grains are shown in a simplified manner.
Referring to FIG. 1C, an active layer 13 is formed by patterning the SLS silicon film 12 by photolithography. Then, a gate insulating layer 14 and a gate electrode 15 are formed on the active layer 13 by a conventional method.
Successively, a source region S and a drain region D are formed by doping the exposed portions of the active layer 13 with impurities. In this case, the source and drain regions S and D become amorphous by the impurity doping, while a channel region C of the SLS crystalline state remains intact as the gate electrode 15 blocks or masks the impurity doping.
Referring to FIG. 1D, the source and drain regions S and D [crystallized by the impurity doping] are crystallized by laser annealing for activation. As a result, the channel region C becomes crystallized by SLS, while the source and drain regions S and D become a polycrystalline state with small size silicon grains.
As mentioned in the above explanation, the source and drain regions of amorphous silicon doped with impurities undergo crystallization by laser activation. In this case, silicon crystallization by the conventional laser annealing fails to form silicon grains of large size by SLS crystallization due to its characteristics.
FIG. 2 shows a result of a silicon film which is activated by a laser of low energy after the silicon film crystallized by SLS has been doped with impurities. As shown in the drawing, the state of the silicon film is amorphous.
FIG. 3 shows another result of a silicon film which is activated by another laser of high energy after the silicon film crystallized by SLS according to the related art has been doped with impurities. As shown in the drawing, it is difficult to apply the silicon film to fabricate devices due to many small-sized silicon grains even though the silicon film is crystallized. As mentioned in the above explanation, source and drain regions of amorphous silicon or polycrystalline silicon of which grain size is small are formed by the related art.
As a result, silicon characteristics of the channel region of the TFT fabricated by the related art differ from those of the impurity region such as the source or drain region, reducing mobility of carriers due to non-uniformity of the characteristics. Thus, characteristics of the TFT become poor.
When activation is carried out by a conventional method of furnace annealing after the impurity doping, re-crystallization of the active layer never occurs since the insulating substrate limits raising of the annealing temperature. Therefore, the source and drain regions remain amorphous, causing problems.
Moreover, it is desirous to simplify the related art which includes a step of crystallizing an initial amorphous silicon and another step of activating an active layer which has become amorphous by the impurity doping.
Accordingly, the present invention is directed to a method of fabricating a thin film transistor that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating a TFT which improves the characteristics of the TFT by carrying out impurity doping of the source and drain regions before the formation of a gate electrode.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the present invention includes the steps of depositing an amorphous silicon film on an insulating substrate, selectively doping the amorphous silicon film with impurities, crystallizing the amorphous silicon film selectively doped with the impurities by sequential lateral solidification, forming an active layer of which doped portions become source and drain regions by patterning the silicon film crystallized by sequential lateral solidification, and forming a gate insulating layer and a gate electrode on the active layer.
In another aspect, the present invention includes the steps of depositing an active layer of amorphous silicon on a substrate, defining source and drain regions in the active layer by selectively doping the active layer with impurities, crystallizing the active layer of amorphous silicon selectively doped with the impurities by sequential lateral solidification, forming a gate insulating layer and a gate electrode on the active layer crystallized by sequential lateral solidification.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.